IP Verification using SV UVM testbench and test cases

UVM Testbench development, Test case development, An example Project, simulation using industry standard simulator

What you’ll learn
Learning Universal Verification Methodology(UVM)
How UVM can be used to build test bench for any digital IP?
Developing Test cases using SV UVM for a digital IP
How to simulate the SV UVM test case

Requirements
Verification principles, Digital fundamentals, Verilog and System Verilog

Description
This course covers the topics, basics of UVM methodology, components, Objects, UVM Factory, configuration, phases, Reports. Step wise approach to build testbench using driver, sequencer, agent, environment, test and top test bench. Building sequences for verifying the features of an example IP. Outcome of this course, one can develop UVM testbench and testcases right from the scratch. The course is also covering an example test bench creation and explains how to write testcases. How to simulate. This is demonstrated with one simulator. This course is useful for Students, who are studying BE/BTech/MTech in Electronics and communication and want to learn UVM, do internship. Also those who have completed Engineering , can opt for this course and learn UVM, simulate with free tools available in edaplayground. This is a complete course with project demonstration and contains the assignments to make the UVM learning easy. The agenda is as follows: Session 01 – UVM OverviewSession 02 – UVM Components and ObjectsSession 03 – TLM Session 04 – UVM FactorySession 05 – UVM ConfigurationSession 06 – UVM PhasesSession 07-1 – UVM ReportSession 07-2 – UVM Report ExampleSession 08 – UVM Sequencer, DriverSession 09 – UVM Agent, MonitorSession 10 – UVM Test, ScoreboardSession 11 – UVM TopologySession 12-1 – Test sequences part 1Session 12-2 – Test sequences part 2Once you go through the course, you can apply and get job in semiconductor companies as design verification engineer.

Overview
Section 1: Introduction

Lecture 1 UVM Overview

Lecture 2 UVM Components and Objects

Lecture 3 Session03-UVM TLM

Lecture 4 Session04-UVM Factory

Lecture 5 UVM Configuration

Lecture 6 UVM Phases

Lecture 7 UVM reports

Lecture 8 UVM Report Example

Lecture 9 UVM Sequencer and Driver

Lecture 10 UVM Monitor and Agent

Lecture 11 UVM Scoreboard, Test, Virtual Sequencer and Testbench top

Lecture 12 UVM Topology and printing

Lecture 13 UVM Sequences-01

Lecture 14 UVM Sequences 02

Lecture 15 UVM Lab exercises

Lecture 16 UVM Project Assignment – APB memory Verification

Lecture 17 Solution for UVM Project Assignment – APB Memory Verification

BE/BTech/ME/M Tech in Electronics and communication,Those want to learn advanced verification methodology for IP verification in ASIC development,Those who wants to do internship in VLSI- Design Verification,To apply for jobs in ASIC Design Verification in Semiconductor companies

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