UVM for Verification Part 2 : Projects

What you’ll learn
Verification of Combinational Circuits
Verification of Sequential Circuits
Verification of Common Bus Protocols viz. APB, AXI
Verification of Communication Protocols viz. UART, SPI, I2C
Understanding usage of Virtual Sequencer, Sequence Library and TLM analysis FIFO

Requirements
Fundamentals of UVM

Description
Writing Verilog test benches is always fun after completing RTL Design. You can assure clients that the design will be bug-free in tested scenarios. As System complexity is growing day by day, System Verilog becomes a choice for verification due to its powerful capabilities and reusability helping verification engineers quickly locate hidden bugs. The System Verilog lags structured approach whereas UVM works very hard on forming a general skeleton. The addition of the configuration database Shifts the way we used to work with the Verification Language in the past. Within a few years, verification engineers recognize the capabilities of UVM and adopted UVM as a defacto standard for the RTL Design verification. The UVM will have a long run in the verification domain hence learning of UVM will help VLSI aspirants to pursue a career in this domain.This is a Lab-based course designed such that anyone with the fundamentals of UVM could understand how verification engineers use UVM to perform verification of commonly used RTLs and sub-blocks in FPGA.  The course covers verification of the combinational circuit like combinational adder, Sequential circuit like Data flip-flop, communication interfaces like a clock generator, UART, SPI, and I2C, and Bus protocols like APB, AXI, and demonstration of few useful UVM concepts like a virtual sequencer, TLM analysis FIFO, and a sequence library.

Who this course is for
Anyone interested in understanding the applications of UVM for verification of Functional behavior of RTL